View MDT10P432P21_8943382.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 1 of 13 2010.8 ver. 1.5 1. general description this 8-bit micro-controller with built-in carrier generator uses a fully static cmos technology to achieve high speed, small size, low power and high noise immunity. on chip memory includes 512 words of rom, and 28 bytes of static ram. 2. features fully cmos static design 8-bit data bus on chip rom size : 512 words internal ram size : 28 bytes (24general purpose registers, 4 special registers) 34 single word instructions 14-bit instructions 2-level stacks operating voltage : 2.0v ~ 5.0 v addressing modes include direct, indirect and relative addressing modes power-on reset internal rc 432k, 440k, 455k, 480khz select in option. system clock : 455khz crystal (osc1 cap 50p; osc2 cap 50p) auto detect external crystal on board . pa0-7 : 8 input only pins with pull-high re sistor and input low wakeup detect circuit. pb0 : cmos output. pb1~7 : seven open drain output pins. built in remote control carrier synthesizer fosc/ 8 (56.9k) or fosc/12 (37.9k ) by firmware setting. option used pb0 nmos without bjt. 4096 clocks for external oscillator start up time. 3. applications remote controller
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 2 of 13 2010.8 ver. 1.5 4. pin assignment p ? pdip, s - psop mdt10p432p11 mdt10p432p13 mdt10p432s11 mdt10p432s13 pa2 1 18 pa1 pa2 1 18 pa5 pa3 2 17 pa0 pa3 2 17 pa4 pa6 3 16 osc1 pa6 3 16 pa1 pa7 4 15 osc2 pa7 4 15 pa0 vss 5 14 vdd vss 5 14 vdd pb0 6 13 pb7 pb0 6 13 pb7 pb1 7 12 pb6 pb1 7 12 pb6 pb2 8 11 pb5 pb2 8 11 pb5 pb3 9 10 pb4 pb3 9 10 pb4 MDT10P432P21 mdt10p432s21 pa5 1 20 pa4 pa2 2 19 pa1 pa3 3 18 pa0 pa6 4 17 osc1 pa7 5 16 osc2 vss 6 15 vdd pb0 7 14 pb7 pb1 8 13 pb6 pb2 9 12 pb5 pb3 10 11 pb4 mdt10p432p31 mdt10p432p35 mdt10p432s31 mdt10p432s35 pa2 1 16 pa1 pa3 1 16 pa2 pa3 2 15 pa0 pa6 2 15 pa1 pa6 3 14 osc1 pa7 3 14 pa0 pa7 4 13 osc2 vss 4 13 vdd vss 5 12 vdd pb0 5 12 pb7 pb0 6 11 pb7 pb1 6 11 pb6 pb1 7 10 pb6 pb2 7 10 pb5 pb2 8 9 pb5 pb3 8 9 pb4
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 3 of 13 2010.8 ver. 1.5 5. order information device rom (words) ram (bytes) i/o package mil remark mdt10p432p11 0.5k 24 14 (6 input; 8 output) 18-dip 300 18 pin ; 6 input (no pa 4~5) ; 8 output mdt10p432p13 0.5k 24 16 (8 input; 8 output) 18-dip 300 18 pin ; 8 input ; 8 output; (no osc1&2) MDT10P432P21 0.5k 24 16 (8 input; 8 output) 20-dip 300 20 pin ; 8 input ; 8 output mdt10p432p31 0.5k 24 12 (6 input; 6 output) 16-dip 300 16 pin ; 6 input (no pa 4&5) ; 6 output (no pb 3&4) mdt10p432p35 0.5k 24 14 (6 input; 8 output) 16-dip 300 16 pin ; 6 input (no pa 4~5) ; 8 output; (no osc1&2) mdt10p432s11 0.5k 24 14 (6 input; 8 output) 18-sop 300 18 pin ; 6 input (no pa 4~5) ; 8 output mdt10p432s13 0.5k 24 16 (8 input; 8 output) 18-sop 300 18 pin ; 8 input ; 8 output; (no osc1&2) mdt10p432s21 0.5k 24 16 (8 input; 8 output) 20-sop 300 20 pin ; 8 input ; 8 output mdt10p432s31 0.5k 24 12 (6 input; 6 output) 16-sop 150 16 pin ; 6 input (no pa 4&5) ; 6 output (no pb 3&4) mdt10p432s35 0.5k 24 14 (6 input; 8 output) 16-sop 150 16 pin ; 6 input (no pa 4~5) ; 8 output; (no osc1&2) 6. block diagram stack two levels program counters rom 51214 instruction register instruction decoder ram 248 special register control circuit status register port a port b data 8bit 9 bits 9 bits 14 bits port pb1~pb7 d0~d7 port pa0~pa7 8 bits port pb0 external xt power on reset power down reset internal rc alu working register
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 4 of 13 2010.8 ver. 1.5 7. pin function description pin name i/o function description pa0~pa7 i port a, ttl input level. built in 50k ohm pull-high resistor. in sleep mode, a high-to-low change on any pin will cause chip reset. pb0 o cmos output pin. enable nmos sink 250ma by option (replace bjt) pb1~pb7 o port b open drain output pins, 50k ohm pull-high resistor. osc1 i crystal oscillation input pin osc2 o crystal oscillation output pin vdd power supply vss ground 8. memory map 8.1 program memory : 000h program memory 1feh 1ffh reset vector 8.2 register map address description 00 indirect addressing register 01 unimplemented 02 pc 03 status 04 msr 05 port a (input only) 06 port b output register 07 unimplemented 08~1f internal ram, general purpose register
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 5 of 13 2010.8 ver. 1.5 (1) iar ( indirect address register) : r0 (2) pc (program counter) : r2 write pc, call --- always 0 ljump, jump, lcall --- from instruction word rtiw, ret --- from stack a9 a8 a7~a0 write pc, jump, call --- from status b5 ljump, lcall --- from instruction word rtiw, ret --- from stack write pc --- from alu ljump, jump, lcall, call --- from instruction word rtiw, ret --- from stack (3) status (status register) : r3 bit symbol function 0 1 2 3 4 5 7 - 6 c hc z /pf /lpt ?? ?? carry bit half carry bit zero bit power loss flag bit low power detect =0 : vdd is lower than 2.1 ~ 2.3v =1 : vdd is higher than 2.1 ~ 2.3v general purpose bit carrier frequency control bits =00 no carrier (default) =01 fosc/8, 1/2 duty =10 fosc/12, 1/2 duty =11 fosc/12, 1/3 duty (1/3 ? hi ; 2/3 - low) (4) msr (memory select register) : r4 (5) port a : r5 bit 7-0 : port a data input (6) port b : r6 bit 7-1 : pb7-pb1 output register (open drain output) bit 0 : pb0 output register (cmos output)
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 6 of 13 2010.8 ver. 1.5 9. reset condition for all registers register address power-on reset iar 00h pc 02h 1111 1111 status 03h 0001 1xxx msr 04h 111x xxxx pb output data 06h 1111 111# note : ? x ? unknown, ? ? ? unimplemented, read as ?0? ? # ? value depends on condition 10. instruction set instruction code mnemonic operands function operating status 010000 00000000 nop no operation none 010000 00000010 sleep sleep mode 0 wt, stop osc tf, pf 010000 00000100 ret return stack pc none 010000 00000rrr cpio r control i/o port register w cpio r none 010001 1rrrrrrr stwr r store w to register w r none 011000 trrrrrrr ldr r, t load register r t z 111010 iiiiiiii ldwi i load immediate to w i w none 010111 trrrrrrr swapr r, t swap halves register [r(0~3) ? r(4~7)] t none 011001 trrrrrrr incr r, t increment register r + 1 t z 011010 trrrrrrr incrsz r, t increment register, skip if zero r + 1 t none 011011 trrrrrrr addwr r, t add w and register w + r t c, hc, z 011100 trrrrrrr subwr r, t subtract w from register r w t (r+/w+1 t) c, hc, z 011101 trrrrrrr decr r, t decrement register r 1 t z 011110 trrrrrrr decrsz r, t decrement register, skip if zero r 1 t none 010010 trrrrrrr andwr r, t and w and register r w t z 110100 iiiiiiii andwi i and w and immediate i w w z 010011 trrrrrrr iorwr r, t inclu. or w and register r w t z 110101 iiiiiiii iorwi i inclu. or w and immediate i w w z 010100 trrrrrrr xorwr r, t exclu. or w and register r ? w t z 110110 iiiiiiii xorwi i exclu. or w and immediate i ? w w z 011111 trrrrrrr comr r, t complement register /r t z
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 7 of 13 2010.8 ver. 1.5 instruction code mnemonic operands function operating status 010110 trrrrrrr rrr r, t rotate right register r(n) r(n-1), c r(7), r(0) c c 010101 trrrrrrr rlr r, t rotate left register r(n) r(n+1), c r(0), r(7) c c 010000 1xxxxxxx clrw clear working register 0 w z 010001 0rrrrrrr clrr r clear register 0 r z 0000bb brrrrrrr bcr r, b bit clear 0 r(b) none 0010bb brrrrrrr bsr r, b bit set 1 r(b) none 0001bb brrrrrrr btsc r, b bit test, skip if clear skip if r(b)=0 none 0011bb brrrrrrr btss r, b bit test, skip if set skip if r(b)=1 none 1000nn nnnnnnnn lcall n long call subroutine n pc, pc+1 stack none 1010nn nnnnnnnn ljump n long jump to address n pc none 110000 nnnnnnnn call n call subroutine n pc, pc+1 stack none 110001 iiiiiiii rtiw i return, place immediate to w stack pc, i w none 11001n nnnnnnnn jump n jump to address n pc none note : w : working register b : bit position cpio : control i/o port register t : target hc : half carry 0 : working register z : zero flag 1 : general register c : carry flag pf : power loss flag r : general register address pc : program counter i : immediate data ( 8 bits ) osc : oscillator n : immediate address inclu. : inclusive ? ? / : complement exclu. : exclusive ? ? ? x : don?t care and : logic and ? ?
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 8 of 13 2010.8 ver. 1.5 11. electrical characteristics (operating temperature at 25 ). sym description condition min typ max unit vdd operating voltage 2.0 6.0 v v il input low voltage pa vdd=5v -0.6 1.0 v v ih input high voltage pa vdd=5v 2.0 vdd+0.6 v i il input leakage current vdd=5v +/-1 a v ol output low voltage pb7~0 pb0 enable 250ma nmos pb0 enable 250ma nmos vdd=5v, i ol =20ma vdd=5v, i ol =5ma vdd=5v, i ol =20ma vdd=5v, i ol =20ma vdd=3v, sink current vdd=2v, sink current 0.6 0.2 0.08 0.03 250 100 v v v v ma ma v oh output high voltage pb0 vdd=5v, i oh = -20ma vdd=5v, i oh = -5ma 2.8 4.2 v v v pr power edge-detector reset voltage 1.8 v
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 9 of 13 2010.8 ver. 1.5 data bus read input resistor port input pad ttl input level pa0~7: pull_hi 50k ttl sleep input low wake_up 12. pa0 ~ pa7 equivalent circuit 13. (a) pb0 equivalent circuit set i/o dffra latch d c rb qb /reset ir carrier port output pad q read data bus 250ma nmos enable s d1 d0 q replace bjt
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 10 of 13 2010.8 ver. 1.5 tris data bus read dffpa latch d c q pb qb reset pb1~7: pull_hi 50k port output pad (b) pb1~7 equivalent circuit 14. application circuit (reference) (a). enable internal 455khz & 250 ma nmos (without bjt) note : power vdd & vss must used metal line to ic vdd & vss with shortest distance ir must used metal line to vdd & pb0 vcc vcc s1 1 2 s2 1 2 s3 1 2 s4 1 2 s5 1 2 s6 1 2 s7 1 2 s8 1 2 s9 1 2 s10 1 2 s11 1 2 s12 1 2 s14 1 2 s15 1 2 s13 1 2 s16 1 2 s17 1 2 s18 1 2 s19 1 2 s20 1 2 s22 1 2 s23 1 2 s21 1 2 s24 1 2 s25 1 2 s28 1 2 s32 1 2 s30 1 2 s26 1 2 s31 1 2 s29 1 2 s27 1 2 s33 1 2 s34 1 2 s35 1 2 s36 1 2 s38 1 2 s39 1 2 s37 1 2 s40 1 2 s41 1 2 s44 1 2 s48 1 2 s46 1 2 s42 1 2 s47 1 2 s45 1 2 s43 1 2 s62 1 2 s64 1 2 s56 1 2 s55 1 2 s52 1 2 s50 1 2 s63 1 2 s60 1 2 s53 1 2 s51 1 2 s49 1 2 s59 1 2 s58 1 2 s57 1 2 s61 1 2 s54 1 2 u1 MDT10P432P21/s21 7 8 9 10 11 12 13 14 18 19 2 3 15 17 16 6 20 1 4 5 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 vdd osc1 osc2 vss pa4 pa5 pa6 pa7 r1 10 10 d1 ir c4 0.1u 1 2 + c3 10u c4 by-pass capacitor must closed the ic vdd and vss
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 11 of 13 2010.8 ver. 1.5 vcc vcc s50 1 2 s64 1 2 s47 1 2 s33 1 2 s11 1 2 s49 1 2 s48 1 2 s55 1 2 s43 1 2 s30 1 2 s42 1 2 s36 1 2 s27 1 2 s26 1 2 s24 1 2 s13 1 2 s12 1 2 s23 1 2 s16 1 2 s9 1 2 s6 1 2 s4 1 2 s38 1 2 s29 1 2 s25 1 2 s21 1 2 s53 1 2 s60 1 2 s45 1 2 s35 1 2 s28 1 2 s17 1 2 10 s54 1 2 s63 1 2 s37 1 2 s8 1 2 s7 1 2 s5 1 2 s3 1 2 s1 1 2 s10 1 2 s41 1 2 s40 1 2 s15 1 2 s61 1 2 s56 1 2 s62 1 2 s39 1 2 s14 1 2 s57 1 2 s52 1 2 s19 1 2 s34 1 2 s31 1 2 s32 1 2 d1 ir s46 1 2 s2 1 2 s58 1 2 s59 1 2 s44 1 2 s18 1 2 r1 10 s51 1 2 s22 1 2 s20 1 2 mdt10p432p13/s13 1 2 3 4 15 16 6 7 8 11 12 13 14 5 9 17 18 10 pa2 pa3 pa6 pa7 pa0 pa1 pb0 pb1 pb2 pb5 pb6 pb7 vdd vss pb3 pa4 pa5 pb4 + c3 10u c4 0.1u 1 2 c4 by-pass capacitor must be closed to the ic vdd and vss vcc vcc s34 1 2 s15 1 2 s53 1 2 s16 1 2 s48 1 2 s6 1 2 s23 1 2 s30 1 2 s47 1 2 s32 1 2 s61 1 2 s41 1 2 s29 1 2 s56 1 2 s63 1 2 s25 1 2 s42 1 2 s55 1 2 s57 1 2 s62 1 2 s9 1 2 s22 1 2 s31 1 2 s13 1 2 s18 1 2 s17 1 2 s40 1 2 s10 1 2 s26 1 2 s2 1 2 s24 1 2 s49 1 2 s50 1 2 s1 1 2 s7 1 2 s54 1 2 s39 1 2 s5 1 2 s58 1 2 s14 1 2 s45 1 2 s38 1 2 s37 1 2 s33 1 2 s64 1 2 s46 1 2 s8 1 2 s21 1 2 mdt10p432 p35/s35 16 1 2 3 14 15 5 6 7 10 11 12 13 4 8 9 pa2 pa3 pa6 pa7 pa0 pa1 pb0 pb1 pb2 pb5 pb6 pb7 vdd vss pb3 pb4 10 d1 ir r1 10 c4 0.1u 1 2 + c3 10u c4 by-pass capacitor must be closed to the ic vdd and vss
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 12 of 13 2010.8 ver. 1.5 (b). enable internal 455khz , disable 250 ma nmos note : power vdd & vss must used metal line to ic vdd & vss with shortest distance vcc vcc s50 1 2 s64 1 2 s47 1 2 s33 1 2 s11 1 2 s49 1 2 s48 1 2 s55 1 2 s43 1 2 s30 1 2 s42 1 2 s36 1 2 s27 1 2 s26 1 2 s24 1 2 s13 1 2 s12 1 2 s23 1 2 s16 1 2 s9 1 2 s6 1 2 s4 1 2 s38 1 2 s29 1 2 s25 1 2 s21 1 2 s53 1 2 s60 1 2 s45 1 2 s35 1 2 s28 1 2 s17 1 2 s54 1 2 s63 1 2 s37 1 2 s8 1 2 s7 1 2 s5 1 2 s3 1 2 s1 1 2 s10 1 2 s41 1 2 s40 1 2 s15 1 2 s61 1 2 s56 1 2 s62 1 2 s39 1 2 s14 1 2 s57 1 2 s52 1 2 s19 1 2 s34 1 2 s31 1 2 s32 1 2 s46 1 2 s2 1 2 s58 1 2 s59 1 2 s44 1 2 s18 1 2 s51 1 2 s22 1 2 s20 1 2 mdt10p432p13/s13 1 2 3 4 15 16 6 7 8 11 12 13 14 5 9 17 18 10 pa2 pa3 pa6 pa7 pa0 pa1 pb0 pb1 pb2 pb5 pb6 pb7 vdd vss pb3 pa4 pa5 pb4 r1 10 q1 npn cbe 1 2 3 10 r2 1k d1 ir + c3 10u c4 0.1u 1 2 c4 by-pass capacitor must be closed to the ic vdd and vss vcc vcc s48 1 2 s10 1 2 s6 1 2 s29 1 2 s1 1 2 s46 1 2 s23 1 2 s31 1 2 s14 1 2 s30 1 2 s26 1 2 d1 ir s56 1 2 s7 1 2 s8 1 2 s13 1 2 s45 1 2 s47 1 2 s2 1 2 s63 1 2 s57 1 2 s54 1 2 s21 1 2 r2 1k s18 1 2 s38 1 2 s32 1 2 s24 1 2 s37 1 2 s25 1 2 s62 1 2 s39 1 2 s17 1 2 s61 1 2 s49 1 2 s33 1 2 s34 1 2 s42 1 2 s9 1 2 s5 1 2 s15 1 2 s40 1 2 q1 npn cbe 1 2 3 s53 1 2 s41 1 2 s50 1 2 s64 1 2 s16 1 2 s55 1 2 s22 1 2 s58 1 2 10 r1 10 c4 0.1u 1 2 mdt10p432p35/s35 16 1 2 3 14 15 5 6 7 10 11 12 13 4 8 9 pa2 pa3 pa6 pa7 pa0 pa1 pb0 pb1 pb2 pb5 pb6 pb7 vdd vss pb3 pb4 + c3 10u c4 by-pass capacitor must be closed to the ic vdd and vss
mdt10p432 this specification is subject to be changed without notice. please visit our web site for the most updated information. http://www.mdtic.com.tw 13 of 13 2010.8 ver. 1.5 (c). disable internal 455khz & 250 ma nmos note : power vdd & vss must used metal line to ic vdd & vss with shortest distance vcc vcc y1 455khz 1 2 c1 50p 1 2 c2 50p 1 2 s1 1 2 s2 1 2 s3 1 2 s4 1 2 s5 1 2 s6 1 2 s7 1 2 s8 1 2 s9 1 2 s10 1 2 s11 1 2 s12 1 2 s14 1 2 s15 1 2 s13 1 2 s16 1 2 s17 1 2 s18 1 2 s19 1 2 s20 1 2 s22 1 2 s23 1 2 s21 1 2 s24 1 2 s25 1 2 s28 1 2 s32 1 2 s30 1 2 s26 1 2 s31 1 2 s29 1 2 s27 1 2 s33 1 2 s34 1 2 s35 1 2 s36 1 2 s38 1 2 s39 1 2 s37 1 2 s40 1 2 s41 1 2 s44 1 2 s48 1 2 s46 1 2 s42 1 2 s47 1 2 s45 1 2 s43 1 2 s62 1 2 s64 1 2 s56 1 2 s55 1 2 s52 1 2 s50 1 2 s63 1 2 s60 1 2 s53 1 2 s51 1 2 s49 1 2 s59 1 2 s58 1 2 s57 1 2 s61 1 2 s54 1 2 r1 10 q1 npn cbe 1 2 3 10 r2 1k d1 ir c4 0.1u 1 2 u1 MDT10P432P21/s21 7 8 9 10 11 12 13 14 18 19 2 3 15 17 16 6 20 1 4 5 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 vdd osc1 osc2 vss pa4 pa5 pa6 pa7 + c3 10u c4 by-pass capacitor must closed the ic vdd and vss

▲Up To Search▲

Price & Availability of MDT10P432P21

	To Download MDT10P432P21 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .